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STV0190
DUAL 40 MSPS 6-BIT ANALOG TO DIGITAL CONVERTER
APPLICATIONS QPSK DEMODULATION IN A SATELLITE DECODER
. . . . . .
ADVANCE DATA
RESOLUTION 6-BIT MAX. SAMPLING FREQUENCY : 40 MSPS TTL DATA OUTPUTS BUILT-IN SAMPLING AND HOLD CIRCUIT DUAL ADC ON CHIP TO IMPROVE CHANNEL MATCHING
DESCRIPTION The STV0190 is a dual 40 MSPS 6-bit Analog to Digital converter. It is dedicated to QPSK demodulation in Satellite receiver. The Flash architecture combined with interpolation technic gives the best trade off between power consumption and maximum conversion speed. PIN CONNECTIONS
VCCO OGND AGND VTO P VINA VMIDA VMIDB VINB VBOT VCCA DGND VCCD CLKIN OGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D5B D4B D3B D2B D1B D0B D5A D4A D3A D2A D1A D0A
SO28 (Plastic Micropackage) ORDER CODE : STV0190
VCCO
May 1996
This is advance information on a new product no w in development or undergoing evaluation. Details are subject to change without notice.
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0190-01.EPS
CLKOUT
STV0190
PIN CONFIGURATION
Pin N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 to 22 23 to 28 Symbol VCCO OGND AGND VTOP VINA VMIDA VMIDB VINB VBOT VCCA DGND VCCD CLKIN OGND VCCO CLKOUT D0A to D5A D0B to D5B Output Buffer Ground Channel A + B Analog Ground Top Reference Voltage Analog Input Channel A Reference Voltage DC Coupling Channel A Reference Voltage DC Coupling Channel B Analog Input Channel B Bottom Reference Voltage Analog Supply Voltage Digital Ground Digital Supply Voltage Clock Input Output Buffer Ground Channel A + B Output Buffer Supply Voltage Channel A + B D0 (LSB) to D5 (MSB) Outputs Channel A D0 (LSB) to D5 (MSB) Outputs Channel B
0190-01.TBL
Function Output Buffer Supply Voltage Channel A + B
Clock Output
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STV0190
BLOCK DIAGRAM
VCCA 10 VCCD 12 VCCO 1 15
S TV0190
VTOP 4 22 D5A
21 D4A
VINA 5
ADC A
TTL OUTP UT LATCHES
20 D3A
19 D2A
18 D1A
17 D0A
VMIDA 6
28 D5B
27 D4B
VINB 8
ADC B
TTL OUTP UT LATCHES
26 D3B
25 D2B
24 D1B
23 D0B 16 CLKOUT VMIDB 7 VBOT 9 3 AGND 11 DGND 2 14 OGND
0190-02.EPS
CLOCK DRIVER
13 CLKIN
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STV0190
ABSOLUTE MAXIMUM RATINGS
Symbol Analog Supply Voltage Digital Supply Voltage Toper Operating Temperature Parameter Value 3.1, 3.45 3.1, 3.45 0, +70 Unit V
o
0190-02.TBL 0190-03.TBL
V C
ELECTRICAL CHARACTERISTICS (VCC = 3.3V, T amb = 0 to 70oC, Full scale 10MHz, 1.5VPP input, 40MSPS, CL = 20pF, unless otherwise specified)
Symbol ANALOG INPUT Differential Reference Voltage Variation of Channel A to Channel B (FS) RIN Input Resistance Input Bandwidth 3dB DIGITAL OUTPUTS High Logic Voltage Low Logic Voltage High Logic Current Low Logic Current Logic Format Analog Input most positive input 2.4 0 -4 4 Digital Output 111111 111110 ............ 100001 100000 011111 011110 ............ 000001 000000 9 5 1 1 4 ns ns ns ns ns VCC 0.4 V V mA mA VTOP - VBOT 0.5 LSB 20 20 1 1.5 8 VPP mV k MHz Parameter Test Conditions Min. Typ. Max. Unit
least positive input tPD tV tSKEW tAPER tR, tF Output Timing Output Timing Data Output Skew TSK (all outputs, settled within 20%) Aperture Delay relative to Data Clock Data Output Rise and Fall Time See Figure 1 See Figure 1 See Figure 1 See Figure 1
63 62 .... 33 32 31 30 .... 1 0
CLOCK INPUT VIH VIL IIH IIL tCL High Input Voltage Low Input Voltage High Input Current Low Input Current Clock Duty Cycle Clock Period See Figure 1 TBD 40 24 60 2.0 0 VCC 0.8 TBD V V A A % ns
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STV0190
ELECTRICAL CHARACTERISTICS (continued)
Symbol CLOCK OUTPUT VOH VOL IOH IOL tCL High Ouput Voltage Low Output Voltage High Output Current Low Output Current Clock Duty Cycle Clock Period REFERENCE LADDER Top Voltage Bottom Voltage DC Bias Restoration Error ZVTOP/VBOT CROSSTALK Isolation A/B DC ACCURACY Integral non Lin. Diff. Non Lin. AC ACCURACY (fIN = 10MHz, FS = 40 MSPS, VIN = 95% FSCALE) Effective Number of Bit SNR THD THD First 5 Harmony Integral non Lin. A/D Amplifier Response Mismatching 5 33 33 -1 +1 0.2 bits dB dB LSB dB
0190-04.TBL 0190-03.EPS
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
2.4 0 -4
VCC 0.4 4
V V mA mA % ns
40 24
60
VCC - 0.5 VCC + 0.5 Open input digital output should be 32/64 011111 90 33/64 100000
V V
Input Impedance
37
dB
-0.5 -0.5
+0.5 +0.5
LSB LSB
Figure 1 : Timing Diagram
N ANALO G S IGNAL tAPER CLOCK OUT S IGNAL tP D DIGITAL S IGNAL tS KEW
Note : This diagram shows a delay of one clock cycle. Additionnal integer multiple delay periods are acceptable. Output data must be valid on the rising edge of the clock out signal.
N+2 N+1 tCL
tV Da ta for N Da ta for N+1 Da ta for N+2
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STV0190
TYPICAL APPLICATION
VCCA 100 100nF 10F VCCD 100nF 10F 10F 100nF VCCO
VTOP 0.1 F 4 VMIDA 0.1 F 6
10
12
1
15
22 21 0V 5 ADC A TTL OUTP UT LATCHES 20 19 18 17 VBOT 9
D5A D4A D3A D2A D1A D0A
0V
VINA
0.1 F
VMIDB 0.1 F 7 28 27 D5B D4B D3B D2B D1B D0B CLKOUT CLKIN
100
0V VINB
0V 8 ADC B
TTL OUTP UT LATCHES
26 25 24 23 16
CLOCK DRIVER
13
S TV0190
3 11 2 14
0190-04.EPS
AGND
DG ND
O GND
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STV0190
PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions A a1 b b1 C c1 D E e e3 F L S
Min. 0.1 0.35 0.23
Millimeters Typ.
Max. 2.65 0.3 0.49 0.32 45 (Typ.)
o
Min. 0.004 0.014 0.009
Inches Typ.
Max. 0.104 0.012 0.019 0.013
0.5 17.7 10 1.27 16.51 7.4 0.4 7.6 1.27 8 (Max.)
o
0.020 18.1 10.65 0.697 0.394 0.050 0.65
SO28TBL
0.713 0.419
0.291 0.016
0.299 0.050
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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PM-SO28.EPS

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